Today's SoCs (System on Chip) and processor products for client, server and mobile applications rely on high speed data communication links in order to communicate large amounts of data across the motherboard or computer/server rack backplane between data sources and destinations. Serial IO (input/output) links (e.g., SERDES, Serializer-Deserializer systems) are among the most common types of high speed IOs in use today, e.g., where a 32 bit (or more) bus is being serialized into a single high speed physical wire-line (e.g., wired) and/or wireless channel. There are many types and families of serial IOs, including PCIe (Peripheral Component Interconnect Express), SATA (Serial ATA), KTI, QPI (QuickPath Interconnect) and wire-line Ethernet links, each with corresponding benefits and characteristics. Links with symbol rates of 5, 8 or 10 GB/sec per physical channel are in relatively wide use, and even higher rates may be possible and are contemplated for commercial use.
In high speed serial data communication links employing NRZ (non-return to zero), PSK (phase shift keying) and PAM (pulse amplitude modulation) modulations, Bit Error Rate (BER), Time-to-Link (TTL) and eye measurements are relatively common metrics for evaluating link performance. A link specification typically includes maximum permissible values for BER and TTL. In order to qualify a link, it must have BER and TTL that are less than these maximums. When designing serial links for high volume systems, merely meeting these criteria is not enough to ensure robust performance over the entire ensemble of scenarios and tolerances that may be experienced in the field. Rather, good design practices suggest that the serial link design include additional operational margins that will ensure performance in degraded conditions. Such margins and their measurement are a central part of a product production quality process.
Link characterization by margining the information bearing signal eye pattern at the receiver decision junction (e.g., at an input to data slicer(s) that are configured to determine whether a signal corresponds to a logic zero or a logic one) is a generally accepted margining method. An eye pattern specification may generally include an eye mask that provides eye opening minimum requirements in order to meet a desired link BER requirement. However, in order to provide a more robust design, communication systems are typically designed to obtain a more desirable performance margin by expanding an area around the eye mask and using the expanded area as the minimum eye opening target.
In order to qualify a link, test data is typically required showing that the link BER is below the specified maximum BER, the time-to-link is below the maximum time-to-link and the eye opening does not impinge on the eye mask. In a relatively low speed SERDES circuit, eye pattern measurements are typically performed very close to an input to a data slicer that makes the decision whether a received bit is a zero or a one. However, in high speed links, accessing this point with external test equipment is generally difficult and may degrade performance. Further, test equipment access is usually limited to the Receiver input terminals (which are not where the actual eye after processing by the receiver may be measured). Thus, high speed data links provide a particular challenge for testing.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art.